OpenAI selects AMD Turin CPUs for Jalapeño

The AI lab pairs its custom inference accelerator with EPYC processors, prioritizing platform maturity and modular sockets over Nvidia Vera.

OpenAI has selected 5th Gen AMD EPYC server processors, codenamed Turin, as host CPUs for rack deployments of its custom Jalapeño inference chip. Richard Ho, vice president and head of hardware at OpenAI, detailed the design choice during an interview with Tom’s Hardware. AMD publicly confirmed the partnership on X on October 6, 2026. The decision puts AMD Turin CPUs at the center of OpenAI’s specialized data center topology, pairing general-purpose x86 compute with in-house neural hardware.

Why the host CPU matters

Accelerators run the matrix multiplications that power large language models, but they cannot operate in isolation. Every production rack needs a host CPU to manage the operating system, feed memory buffers, and route high-speed networking traffic. In high-density server racks, communication between the host processor and accelerator modules determines whether compute engines stay fed or sit idle waiting on data.

OpenAI’s node architecture, named Katsu, pairs two AMD Turin processors with 1.5 terabytes of system memory per tray. Eight high-speed PCIe direct-attach copper cables link each host tray directly to the Jalapeño accelerator enclosures, minimizing interconnect latency without requiring complex active retimers.

Choosing AMD Turin CPUs over Nvidia Vera

The decision to use AMD chips drew immediate attention across the semiconductor industry because OpenAI bypassed Nvidia’s standalone Vera CPU. Ho explained that the engineering team prioritized speed to production and supply chain predictability. Established server manufacturers already possessed extensive tooling and firmware validation for AMD’s SP5 socket ecosystem.

“The way we approached this design was really in terms of de-risking and being able to do this design fast,” Ho told Tom’s Hardware. “Vera as a standalone is a little bit behind on that maturity level. The Turin device is strong. It did what we needed to do, and partly our partners had experience with it.”

Mechanical servicing factored into the decision as well. AMD EPYC processors seat into standard motherboard sockets. When a single processor develops a fault, technicians can swap the component on-site in minutes. Nvidia’s Vera architecture relies on soldered board-level integration, which forces data center operators to replace entire multi-component board assemblies during hardware failures.

Inside the Jalapeño accelerator

Jalapeño is an application-specific integrated circuit (ASIC) built strictly for running trained AI models at scale. Co-developed with Broadcom, the project moved from register-transfer level design to final tapeout in nine months, completing in November 2025. The chip packs 216 gigabytes of HBM4 memory, delivers up to 15.4 terabytes per second of memory bandwidth, and operates within a 700-watt thermal design power budget.

OpenAI reported internal benchmark improvements of 1.5x to 1.9x in compute operations per watt and latency reductions between 1.7x and 3.6x when serving models such as GPT-OSS, DeepSeek R1, and Kimi K2.5. Because those performance numbers come entirely from internal company testing rather than third-party hardware audits, independent verification is not yet available. AMD also has a commercial stake in highlighting the win publicly.

What remains unconfirmed

OpenAI has not disclosed total production volumes for Jalapeño or the number of Turin host nodes deployed in active data centers. The specific EPYC 9005 processor models remain unannounced, leaving open whether the clusters rely on standard Zen 5 cores or dense Zen 5c variants. The hosting facilities running the hardware, whether Microsoft Azure, Oracle Cloud Infrastructure, or dedicated private data centers, also remain undisclosed. OpenAI stated that its hardware division continues to test competing processors for future revisions.